The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. Because of the high precision required in the production of these integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures being created on the wafer surface. As the size of integrated circuits continues to decrease and the number of microstructures per integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
For a discussion of chemical mechanical planarization (CMP) processes and apparatus, see, for example, Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud, et al., U.S. Pat. No. 5,329,732, issued July, 1994; Karlsrud et al., U.S. Pat. No. 5,498,196, issued March, 1996; and Karlsrud, et al., U.S. Pat. No. 5,498,199, issued March, 1996.
Such polishing is well known in the art and generally includes attaching one side of the wafer to a flat surface of a wafer carrier or chuck and pressing the other side of the wafer against a flat polishing surface. In general, the polishing surface includes a polishing pad that has an exposed abrasive surface of, for example, cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives. During the polishing or planarization process, the workpiece or wafer is typically pressed against the polishing pad surface while the pad rotates about its vertical axis. In addition, to improve the polishing effectiveness, the wafer may also be rotated about its vertical axis and oscillated back and forth over the surface of the polishing pad.
Many semiconductor workpieces require multiple polishing steps, e.g., an aggressive material removal step followed by one or more buffing or final polishing steps. Due to the different layers that may be present in the workpiece and the different goals of the various processing steps, a number of different polishing pads and/or polishing slurries may be utilized during a CMP procedure. Consequently, many conventional CMP systems utilize a number of distinct polishing pads, each respectively mounted to a separate rotatable polishing table. To accommodate a plurality of polishing tables, such CMP systems often require an undesirably large operating area. Unfortunately, many semiconductor manufacturing facilities lack the large amount of free floor space required for large CMP machines. In addition, the footprint of such machines should be kept to a minimum because floor space is expensive within the clean room environment.
The need for compact CMP machines may increase with the demand for large semiconductor wafers (e.g., twelve inches in diameter or larger). To achieve effective planarization and polishing of twelve-inch wafers, the CMP polishing pads should be appropriately sized. Accordingly, any footprint restrictions will become increasingly difficult to meet with a CMP machine that utilizes a plurality of unstacked and distinct polishing pads.
Clover, U. S. Pat. No. 5,554,065, issued Sept. 10, 1996, discloses a vertically stacked planarization machine that is intended to provide a physically compact system capable of processing semiconductor wafers. Unfortunately, this machine requires a complex control system that employs an elevator assembly and an intricate cam mechanism for rotating the stacked polishing pads. Thus, while the vertically stacked arrangement may conserve some space otherwise reserved for polishing pads arranged in a horizontal configuration, vertical and horizontal space is sacrificed to accommodate the elevator assembly, control elements, and rotating mechanism. Furthermore, the use of many individual polishing pads to accommodate a higher throughput may yield undesirably nonuniform results from wafer to wafer, and the complex control system may not otherwise function in a sufficiently robust and consistent manner.
The prior art lacks a practical space-saving solution for existing CMP systems that utilize a plurality of horizontally disposed polishing pads. High quality CMP systems can cost millions of dollars; it may not be economical to replace an existing system with an entirely new system or to retrofit an existing system with complicated hardware upgrades. It may also be uneconomical to modify an existing CMP machine to accommodate one or more additional polishing pads without increasing the footprint of the machine.